Sunday, 20 November 2011 06:38

N type wafers, new developments in wafering, new module expectations

Written by 

In our introduction to production of ingots, we learned that n- type polysilicon is produced by adding phosphorus into the crucible

We have touched on two areas of technology advancement. Cell structures which will lead to better conversion link below

 and material development in a form of quasi mono polysilicon, which will offer high conversion at the lower cost of production

The next step is a combination of productivity leading to reduction of cost and further review of n type wafer, as future of the higher conversion. 

N-type wafers

In our introduction to production of ingots, we learned that n- type polysilicon is produced by adding phosphorus into the crucible. This is a lot more difficult than adding boron, since boron has a low segregation coefficient which makes it easier to make p-type boules.  Introduction of boron in diffusion step when creating a cell is also harder. New techniques like ion implantation can replace traditional diffusion by doping as a well as change from silicon nitrade to another passivation agent like aluminium oxide through CVD or ALD systems is required.  Overall based on complex data n-type wafers are a lot more prone to produce high conversion particularly out of the monocrystalline silicon versus the multicrystalline one.  In case of the n-type mono cells the LID effect (light induced degradation) is almost eliminated.  Since monocrystalline silicon is already obvious choice in higher conversion, there will be other technological advances like continuous production in Cz process discussed by the GT Technologies eliminating batching process.  Delivering even better purity per average batch will add to better conversion.

Wafering, diamond sawing and big load ingots

Ultimately the reduction of poly silicon in the wafer is the holy grail of any producer. The amount of the polysilicon has inclusion of the loss of material due to kerf.  EU SRA has published interesting road map recently and sees thickness to move below 150 microns from current 180-200 microns in next 5 years. The consumption of the silicon per watt will be at 5 to below 5 grams per watt or less when combined less kerf and less thickness.  Use of the processing equipment will also influence the output. One of the critical points preventing lower thickness of the wafer is the aftermath of handling for the purpose of cell processing and to limit the breakage.  Even the module glass application process when seen to improve cost by use of the thinner glass poses a potential problem for protecting a thinner wafer. The safest approach is to work on reduction of kerf to save the material waste.  The next opportunity is seen in the diamond coated wire versus a steel wire. GCL has been including diamond saw on more frequent basis. The results provide for no cost on slurry and there are 50% gains on productivity of the diamond wire in the cutting process. When time is the essential diamond sawing is an exceptional alternative. However drawback is in the cost of the auxiliary material and the replacement value. Another influential processing improvement is the size of the ingot and operational table to accept larger loads to produce more bricks for wafering.  Reduction of touches minimizes the operational time and increases a yield from the hourly performance.  In combination of DSS furnaces now capable producing 1000 Kg ingots manufacturers like Meyer Burger or Applied Materials have pushed for the ability to accommodate big loads and essentially double the yearly production and through it reduced costs.  Some organizations experiment with even larger ingot sizes  and that path may continue for some time.

Module material improvements

Based on the same EU SRA study, certain module improvements are required to accommodate the changes in the cell structure or the introduction of thinner wafers.

To list few shallow emitter or selective emitter will require better light transmission through glass or encapsulant (EVA -Ethylene vinyl acetate). New metallization like copper will require alternative interconnection technologies. Heterojunction will be based on moisture proof components and low melt temperature contacting.  New back circuit sheets for IBC or all in back contact cells. Encapsulants protecting from mechanical damages with added optical qualities will be formulated for ever thinner wafers. Antireflective glass coatings to create better conversion to limit or eliminate CTM (cell to module loss of conversion).  Ultimately the existing processes will become evaluated and moved to low impact and automation. Overall improvements will lead to 30 years guaranteed lifetime from current 25 years.



Read 1413 times Last modified on Monday, 07 October 2013 03:06
Robert Dydo

Robert is the founder and CEO of SolarPVInvestor and SPVInvestor Research, Inc. His career spans more than 20 years in supply chain, managing and planning operations for distribution centers. An ardent private investor, Robert found his niche in contesting misinformation about solar in general, and the Chinese solar industry in particular, while using his finance education matched with a lifelong ardor for the stock market

SPVInvestor Research, a Canadian incorporated research firm. We publish CEDR, the most complete, monthly report on exports of modules, cells, wafer from China, including focus on US-listed Chinese companies.